Telephone switching systems have been equipped with redundant clock circuits to prevent interruptions in service due to failure of a clock circuit. These telephone systems typically include a pair of clock circuits arranged in an active-standby manner. Such an arrangement is based on the assumption that only one fault can exist at one time and therefore two clock circuits were deemed sufficient. Only minimal logic circuitry was needed to control selection of active and standby clock circuits, since such circuitry was only required to detect failure of the active clock circuit and then switch to the standby clock circuit. However, such systems are subject to interruptions in service, if there is a failure in the standby clock circuit, which is forced on line upon detection of a failure in the active clock circuit.
In order to provide increased reliability additional clock circuits and more sophisticated clock selection circuitry are required. An example of such a sophisticated clock selection circuit, and associated multiple clock circuits, is disclosed in U.S. Pat. No. 4,322,580, issued to A. R. Khan, et al, on Mar. 30, 1982. That clock selection circuit insures that only a properly operating standby clock circuit is switched on-line upon detection of a failure in the active clock circuit. However, that arrangement is susceptible to erroneous operation in the event of a processor communication link failure, or power-up/power-down operations.
Accordingly, it is the object of the present invention to provide a novel, highly reliable clock selection control circuit.